The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Mar. 25, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jui-Jen Wu, Hsinchu, TW;

Win-San Khwa, Hsinchu, TW;

Jen-Chieh Liu, Hsinchu, TW;

Meng-Fan Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 7/06 (2006.01); G11C 7/08 (2006.01);
U.S. Cl.
CPC ...
G11C 7/065 (2013.01); G11C 7/08 (2013.01);
Abstract

A circuit includes first and second data lines, a sense amplifier including first and second input terminals, a first p-type metal-oxide-semiconductor (PMOS) transistor coupled in series with a first capacitive device between the first data line and the second input terminal, a second PMOS transistor coupled in series with a second capacitive device between the second data line and the first input terminal, a third PMOS transistor coupled between the first data line and the first input terminal, a fourth PMOS transistor coupled between the second data line and the second input terminal, a first n-type metal-oxide-semiconductor (NMOS) transistor configured to selectively couple each of the first PMOS transistor and the first capacitive device to a ground node, and a second NMOS transistor configured to selectively couple each of the second PMOS transistor and the second capacitive device to the ground node.


Find Patent Forward Citations

Loading…