Channel pre-charge process in a memory device

Abstract

The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.