The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Feb. 10, 2022
Applicant:

SK Keyfoundry Inc., Cheongju-si, KR;

Inventors:

Youngchul Seo, Gwangmyeong-si, KR;

Weon-Hwa Jeong, Seoul, KR;

Yonghwan Kim, Cheongju-si, KR;

Chulgeun Lim, Gunsan-si, KR;

Hoon Jin, Cheongju-si, KR;

Sungbum Park, Seongnam-si, KR;

Keesik Ahn, Hwaseong-si, KR;

Assignee:

SK keyfoundry Inc., Cheongju-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01); H10B 41/30 (2023.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0433 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); H10B 41/30 (2023.02); G11C 16/14 (2013.01);
Abstract

An embedded flash memory and an operation method thereof is provided. The embedded flash memory includes a memory cell array comprising a plurality of memory cells, an automatic verification controller comprising: a TRIM calibration configured to provide a write voltage, and a time controller configured to control a write time, and a high voltage generator configured to provide the write voltage to the memory cell array, an input buffer configured to store input data, a sense amplifier configured to generate read data from the memory cell array, and a data comparator configured to compare the read data with the input data.


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