The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2025
Filed:
Jun. 13, 2024
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Pochun Wang, Hsinchu, TW;
Jerry Chang Jui Kao, Taipei, TW;
Jung-Chan Yang, Taoyuan, TW;
Hui-Zhong Zhuang, Kaohsiung, TW;
Tzu-Ying Lin, Hsinchu, TW;
Chung-Hsing Wang, Hsinchu County, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.