The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2025
Filed:
May. 26, 2022
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Alexander Rabinovitch, Shrewsbury, MA (US);
Baijayanta Ray, Bangalore, IN;
Assignee:
Synopsys, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 9/455 (2018.01); G06F 30/331 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 9/455 (2013.01); G06F 30/331 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01);
Abstract
Emulating a circuit design includes remodeling the clock signals of the circuit design. A circuit design includes clock signals that are based on a root clock signal. The clock signals are analyzed to identify a first clock signal of the clock signals that is faster than a second clock signal of the clock signals. The second clock signal is remodeled based on the first clock signal. An updated circuit design is generated based on remodeled second clock signal, and operation of the updated circuit design is emulated.