The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Nov. 03, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Dmitri A. Yudanov, Rancho Cordova, CA (US);

Shanky Kumar Jain, Folsom, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G06F 3/06 (2006.01); G06F 9/54 (2006.01); G06F 12/02 (2006.01); G06F 12/0802 (2016.01); G06F 12/0873 (2016.01); G06F 12/0875 (2016.01); G06F 12/0893 (2016.01); G06F 12/1045 (2016.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 9/546 (2013.01); G06F 12/0246 (2013.01); G06F 12/0802 (2013.01); G06F 12/0873 (2013.01); G06F 12/0875 (2013.01); G06F 12/0893 (2013.01); G06F 12/1045 (2013.01); G11C 7/08 (2013.01); G11C 7/1012 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 8/08 (2013.01); G11C 11/221 (2013.01); G11C 11/2257 (2013.01); G11C 11/2259 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/2297 (2013.01); G11C 11/406 (2013.01); G11C 11/40603 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G06F 2212/60 (2013.01); G06F 2212/608 (2013.01); G06F 2212/72 (2013.01); G06F 2212/7201 (2013.01);
Abstract

Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.


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