The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Jun. 30, 2023
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Andrea Costa, Delta, CA;

Frederic Jean Neuveux, Grenoble, FR;

Salvatore Talluto, Gavirate, IT;

Sorin Ioan Popa, Saint-Ismier, FR;

Leela Krishna Thota, Bangalore, IN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3181 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01); G01R 31/31704 (2013.01); G01R 31/31813 (2013.01);
Abstract

A block of circuitry contains at least one sub-block. Test patterns for the sub-block (sub-level test patterns) include sub-level test stimuli and corresponding sub-level test responses. These are ported to the block-level to produce block-level test patterns, block-level test stimuli, and block-level test responses. The block-level test patterns are validated as follows. Propagation of the block-level test stimuli through the block-level design is computed. The signals produced by such computed propagation at the sub-block inputs are compared against the sub-level test stimuli, and the signals produced by such computed propagation at the block outputs are compared against the block-level test responses.


Find Patent Forward Citations

Loading…