The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Jan. 26, 2022
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Dengfeng Ji, Shanghai, CN;

Yi Jin, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H01L 21/321 (2006.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 84/834 (2025.01); H01L 21/3212 (2013.01); H10D 64/017 (2025.01); H10D 64/258 (2025.01); H10D 64/518 (2025.01); H10D 84/013 (2025.01); H10D 84/0142 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, first gate structures, second gate structures, first source-drain doped layers, second source-drain doped layers, and a first dielectric layer. A top surface of the first dielectric layer disposed over the first region is lower than a top surface of the first dielectric layer disposed over the second region. The semiconductor structure also includes a first barrier layer disposed over the first dielectric layer disposed over the first region. The first barrier layer and the first dielectric layer disposed over the first region include a first opening exposing the first source-drain doped layer, and the first dielectric layer disposed over the second region includes a second opening exposing the second source-drain doped layer.


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