The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Jan. 04, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Josh Lin, Tainan, TW;

Chia-Ta Hsieh, Tainan, TW;

Chen-Ming Huang, Tainan, TW;

Chi-Wei Ho, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/30 (2023.01); H01L 21/768 (2006.01); H10B 41/10 (2023.01); H10B 41/40 (2023.01); H10B 41/42 (2023.01); H10D 30/68 (2025.01); H10D 64/01 (2025.01); H01L 23/485 (2006.01);
U.S. Cl.
CPC ...
H10B 41/30 (2023.02); H01L 21/76802 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H10B 41/10 (2023.02); H10B 41/40 (2023.02); H10B 41/42 (2023.02); H10D 30/6891 (2025.01); H10D 64/015 (2025.01); H01L 23/485 (2013.01); H10D 64/021 (2025.01);
Abstract

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a first conductive structure over a substrate. A first intermediate sidewall spacer is formed to surround the first conductive structure. A masking material is formed over the substrate and around the first intermediate sidewall spacer. A part of the first intermediate sidewall spacer protrudes outward from the masking material. The part of the first intermediate sidewall spacer that protrudes outward from the masking material is etched to form a first sidewall spacer.


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