The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Jun. 22, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Raghavendra Rao, Bangalore, IN;

Ranjul Balakrishnan, Bangalore, IN;

Shailendra Singh Chauhan, Bengaluru, IN;

Sandesh Krishnamurthy Geejagaaru, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/14 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 1/111 (2013.01); H05K 1/141 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10545 (2013.01);
Abstract

A memory module has pads on the top and bottom surfaces of a module printed circuit board (PCB). The pads match the pin layout of one or more memory devices to be mounted on the memory module. The pads on one surface of the PCB electrically interconnect to the memory device(s), and the pads on the other surface electrically interconnect to pads on a system board, such as a motherboard. With the pad layout on the memory module, the pad layout of the system board can be the same for a memory-down implementation and for a removable memory module. The pad layout provides good signal-to-noise performance and can enable a memory module for low power double data rate (LPDDR) memory, double data rate (DDR) memory, and graphics double data rate (GDDR) memory.


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