The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2025
Filed:
Nov. 09, 2020
Applicant:
Hamamatsu Photonics K.k., Hamamatsu, JP;
Inventors:
Assignee:
HAMAMATSU PHOTONICS K.K., Hamamatsu, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/687 (2006.01); H01L 21/67 (2006.01); H01L 21/677 (2006.01);
U.S. Cl.
CPC ...
H01L 21/68728 (2013.01); H01L 21/67288 (2013.01); H01L 21/67706 (2013.01); H01L 21/68721 (2013.01);
Abstract
A failure analysis unit is a wafer conveyance unit configured to convey a wafer while holding the wafer in a semiconductor failure analysis apparatus, the wafer conveyance unit including: a placement table configured to fix a wafer at a predetermined observation position; and a wafer chuck configured to convey the wafer while holding the wafer to the observation position. The wafer chuck includes a plurality of holding members (protruding portions) provided so as to face a side surface of the wafer, and holds the wafer by sandwiching a peripheral portion of the wafer W with the plurality of holding members.