The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2025
Filed:
Apr. 28, 2023
Silicon Storage Technology, Inc., San Jose, CA (US);
The Regents of the University of California, Oakland, CA (US);
Hieu Van Tran, San Jose, CA (US);
Nhan Do, Saratoga, CA (US);
Farnood Merrikh Bayat, Goleta, CA (US);
Xinjie Guo, Goleta, CA (US);
Dmitri Strukov, Goleta, CA (US);
Vipin Tiwari, Dublin, CA (US);
Mark Reiten, Alamo, CA (US);
Silicon Storage Technology, Inc., San Jose, CA (US);
The Regents of the University of California, Oakland, CA (US);
Abstract
A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns. Respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other. Respective ones of first lines electrically connect together the source regions in one of the rows of the source regions and are electrically isolated from the source regions in other rows of the source regions. Respective ones of second lines electrically connect together the first drain regions of one of the columns of drain regions and are electrically isolated from the second drain regions of the one column of drain regions. Respective ones of third lines electrically connect together the second drain regions of one of the columns of drain regions and are electrically isolated from the first drain regions of the one column of drain regions.