The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Dec. 27, 2023
Applicant:

Industrial Technology Research Institute, Hsinchu, TW;

Inventors:

Haw-Tyng Huang, Taipei, TW;

Po-Chun Yeh, Taichung, TW;

Hsien-Yi Liao, Taichung, TW;

Yao-Cing Han, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/121 (2023.01); G09G 3/3233 (2016.01); H10D 30/01 (2025.01); H10D 30/63 (2025.01); H10D 30/67 (2025.01); H10D 62/17 (2025.01); H10D 84/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/12 (2023.01); H10K 59/124 (2023.01); H10D 30/60 (2025.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); G09G 3/3233 (2013.01); H10K 59/1201 (2023.02); H10K 59/124 (2023.02); H10D 30/025 (2025.01); H10D 30/60 (2025.01); H10D 30/63 (2025.01); H10D 30/6735 (2025.01); H10D 30/6755 (2025.01); H10D 62/292 (2025.01); H10D 84/016 (2025.01); H10D 84/0195 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01);
Abstract

An all-oxide transistor structure includes a substrate having an upper surface and a first transistor disposed on the upper surface of the substrate. The first transistor includes a first drain, a first dielectric layer, a first source, at least one first opening and a first channel layer. The first drain, the first dielectric layer and the first source are disposed on the substrate along a first direction, and the first direction is parallel to a normal direction of the upper surface. The first opening passes through the first drain, the first dielectric layer and the first source along the first direction. The first channel layer, the first gate dielectric layer and the first gate are disposed in the first opening. The first gate dielectric layer is disposed on the first channel layer. The first gate is disposed on the first gate dielectric layer.


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