The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Jan. 14, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Yiming Zhu, Hefei, CN;

Erxuan Ping, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/18 (2006.01); H10B 12/00 (2023.01); H10B 51/40 (2023.01); H10B 53/40 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
G11C 7/18 (2013.01); H10B 12/482 (2023.02); H10B 51/40 (2023.02); H10B 53/40 (2023.02); H10B 61/20 (2023.02); H10B 63/34 (2023.02);
Abstract

A semiconductor structure and a method for forming the same, and a memory and a method for forming the same are provided. The method for forming the semiconductor structure includes: providing a substrate, in which a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate; patterning the active layer and the sacrificial layer to form grooves which divide the active layer and the sacrificial layer into a plurality of active areas; filling the grooves to form a first isolation layer surrounding the active areas; patterning the active layer in the active areas to form a plurality of separate active patterns; removing the sacrificial layer via openings between adjacent active patterns to form gaps between bottoms of the active patterns and the substrate; forming bit lines in the gaps; and forming semiconductor pillars on partial tops of the active patterns.


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