The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Jan. 03, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yen-Jui Chiu, Hsinchu, TW;

Yao-Teng Chuang, Hsinchu, TW;

Kuei-Lun Lin, Keelung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/67 (2025.01); H10D 86/01 (2025.01);
U.S. Cl.
CPC ...
H10D 64/017 (2025.01); H10D 64/01 (2025.01); H10D 86/0221 (2025.01); H10D 86/0231 (2025.01); H10D 30/6735 (2025.01);
Abstract

A method includes following steps. A first gate dielectric layer is deposited over a first semiconductor channel and a second semiconductor channel. A second gate dielectric layer is deposited over the first gate dielectric layer. A layer is formed over the second gate dielectric layer using atomic layer deposition (ALD) cycles each comprising sequentially performing a first pulse step for a first pulse time, a first purge step for a first purge time, a second pulse step for a second pulse time, and a second purge step for a second purge time. A ratio of the first purge time to the first pulse time is greater than a ratio of the second purge time to the second pulse time. The layer is patterned to expose a portion of the second gate dielectric layer. The exposed portion of the second gate dielectric layer is etched.


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