The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Jun. 28, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Yen-Tsai Yi, Tainan, TW;

Wei-Chuan Tsai, Changhua County, TW;

Jin-Yan Chiou, Tainan, TW;

Hsiang-Wen Ke, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 23/31 (2006.01); H01L 29/08 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/85 (2025.01); H10D 64/62 (2025.01); H10D 64/64 (2025.01); H10D 30/47 (2025.01);
U.S. Cl.
CPC ...
H10D 62/343 (2025.01); H01L 23/3171 (2013.01); H10D 30/015 (2025.01); H10D 30/6738 (2025.01); H10D 30/675 (2025.01); H10D 62/151 (2025.01); H10D 62/161 (2025.01); H10D 62/85 (2025.01); H10D 62/8503 (2025.01); H10D 64/62 (2025.01); H10D 64/64 (2025.01); H10D 30/4732 (2025.01);
Abstract

A method for fabricating high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a titanium nitride (TiN) layer on the p-type semiconductor layer as a nitrogen to titanium (N/Ti) ratio of the TiN layer is greater than 1, forming a passivation layer on the TiN layer and the barrier layer, removing the passivation layer to form an opening, forming a gate electrode in the opening, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode on the barrier layer.


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