The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Feb. 06, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

I-Sheng Chen, Taipei, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Cheng-Hsien Wu, Hsinchu, TW;

Ling-Yen Yeh, Hsinchu, TW;

Carlos H. Diaz, Los Altos Hills, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); B82Y 10/00 (2011.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/62 (2025.01); B82Y 10/00 (2013.01); H01L 21/76877 (2013.01); H10D 30/014 (2025.01); H10D 30/023 (2025.01); H10D 30/024 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/116 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 84/0158 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01); H10D 88/00 (2025.01); H10D 88/01 (2025.01); H10D 84/0128 (2025.01); H10D 84/014 (2025.01); H10D 84/0177 (2025.01); H10D 84/0179 (2025.01);
Abstract

A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, a gate conductive structure over the gate dielectric layer, and a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures. The first insulating spacer is in direct contact with the gate conductive structure and the gate dielectric layer.


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