The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Aug. 08, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chen-Jun Wu, Hsinchu, TW;

Sun Yi Chang, New Taipei, TW;

Sheng-Chih Lai, Hsinchu, TW;

Chung-Te Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/16 (2006.01); G11C 11/22 (2006.01); G11C 13/00 (2006.01); G11C 16/08 (2006.01); H10B 41/30 (2023.01); H10B 43/30 (2023.01); H10B 51/30 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H10B 43/30 (2023.02); G11C 11/1657 (2013.01); G11C 11/2257 (2013.01); G11C 13/0028 (2013.01); G11C 16/08 (2013.01); H10B 41/30 (2023.02); H10B 51/30 (2023.02); H10B 61/22 (2023.02); H10B 63/30 (2023.02);
Abstract

A memory cell array is provided. The memory cell array includes: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines electrically connected to the plurality of rows, respectively; a plurality of source lines electrically connected to the plurality of columns, respectively; and a plurality of bit lines electrically connected to the plurality of columns, respectively. A plurality of inactivated word lines are configured to be applied a bias voltage that is zero, and the plurality of source lines are configured to be applied a positive bias voltage.


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