The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Aug. 01, 2023
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Gaurav Agrawal, Noida, IN;

Deependra Kumar Jain, Noida, IN;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/081 (2006.01); H03L 7/083 (2006.01); H03L 7/193 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0818 (2013.01); H03L 7/083 (2013.01); H03L 7/193 (2013.01);
Abstract

A digital frequency synthesizer includes a delay-locked loop (DLL) that generates time-delayed versions of a reference clock signal, a clock divider that executes an integer-division operation on one delayed clock signal to generate an integer-divided clock signal, and control circuitry that generates fractional data for enabling a fractional division. The digital frequency synthesizer further includes a first clock selector that selects one delayed clock signal as a DLL clock signal based on the fractional data, a delay chain that generates time-delayed versions of the DLL clock signal, and a second clock selector that selects one delayed clock signal as a selected clock signal based on the fractional data. A rising edge of the integer-divided clock signal is adjusted based on the selected clock signal to generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.


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