The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Dec. 12, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jinnam Kim, Suwon-si, KR;

Seokho Kim, Suwon-si, KR;

Hoonjoo Na, Suwon-si, KR;

Kwangjin Moon, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 25/18 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/06541 (2013.01);
Abstract

A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.


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