The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Feb. 01, 2024
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventor:

Chien-Ming Lai, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); H01L 24/05 (2013.01); H01L 24/80 (2013.01); H01L 2224/05016 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/351 (2013.01);
Abstract

A semiconductor structure for wafer level bonding includes an interconnecting layer on a substrate, a bonding dielectric layer on the interconnecting layer, and a bonding pad in the bonding dielectric layer. The bonding pad includes a top surface exposed from the bonding dielectric layer, a bottom surface opposite to the top surface and physically contacting a dielectric portion of the interconnecting layer, and a sidewall between the top surface and the bottom surface. A bottom angle between the sidewall and the bottom surface is smaller than 90 degrees, and the bonding pad is not electrically connected to the interconnecting layer.


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