The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Jul. 19, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Yi-Ren Wang, New Taipei, TW;

Yuan-Chih Hsieh, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C23C 16/04 (2006.01); C23C 16/34 (2006.01); C23C 16/40 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0217 (2013.01); C23C 16/04 (2013.01); C23C 16/345 (2013.01); C23C 16/401 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/3213 (2013.01);
Abstract

A layer stack is formed over a conductive material portion located on a substrate. The layer stack contains a first silicon oxide layer, a silicon nitride layer formed by chemical vapor deposition, and a second silicon oxide layer. A patterned etch mask layer including an opening is formed over the layer stack. A via cavity extending through the layer stack and down to the conductive material portion is formed by isotropically etching portions of the layer stack underlying the opening in the patterned etch mask layer using an isotropic etch process. A buffered oxide etch process may be used, in which the etch rate of the silicon nitride layer is less than, but is significant enough, compared to the etch rate of the first silicon oxide layer to provide tapered straight sidewalls on the silicon nitride layer. An optical device including a patterned layer stack can be provided.


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