The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Jun. 06, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yen Lin Chung, Hsinchu, TW;

Kao-Cheng Lin, Hsinchu, TW;

Wei Min Chan, Hsinchu, TW;

Yen-Huei Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 10/00 (2023.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 10/125 (2023.02); G11C 11/419 (2013.01);
Abstract

A memory cell includes a first, second, third, and fourth transistor, a first and a second inverter, and a first and second word line. The first inverter is coupled to the first and third transistor. The second inverter is coupled to the first inverter and the first and third transistor. The first word line is configured to supply a first word line signal, is on a first metal layer above a front-side of a substrate, and is coupled to the first and third transistor. The second word line is configured to supply a second word line signal, and is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and is coupled to the second and fourth transistor. At least the first, second, third or fourth transistor are on the front-side of the substrate.


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