The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Aug. 30, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Erik T. Barmon, Boise, ID (US);

Yang Lu, Boise, ID (US);

Nathaniel J. Meier, Boise, ID (US);

Kang-Yong Kim, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/408 (2006.01); G06F 12/06 (2006.01); G11C 7/24 (2006.01); G11C 29/18 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G11C 11/408 (2013.01); G06F 12/06 (2013.01); G11C 7/24 (2013.01); G11C 29/18 (2013.01); G11C 29/56004 (2013.01);
Abstract

Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.


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