The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Sep. 06, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Erik V. Pohlmann, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G11C 7/22 (2006.01); G11C 11/406 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/04 (2013.01); G11C 7/222 (2013.01); G11C 11/40615 (2013.01); G11C 11/4093 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01);
Abstract

Methods, systems, and devices for maximum memory clock estimation procedures are described. For instance, a device, such as a host device, may truncate a value of a first parameter associated with a first duration for a clock coupled with a memory array to perform a clock cycle and may estimate a value of a second parameter that is inversely proportional to the truncated value of the first parameter. The device may determine a quantity of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based on adjusting the second parameter. The device may access the one or more memory cells of the memory array based on the determined quantity of clock cycles associated with the maximum duration.


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