Ferroelectric memory operation bias and power domains

Abstract

A memory system including a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The plurality of memory cells are arranged in rows and columns, each of the plurality of memory cells having a gate, a drain, and a source. In the plurality of word lines, each of the word lines having a corresponding row, wherein each of the word lines is coupled to the gates of the memory cells in the corresponding row. In the plurality of bit lines and the plurality of source lines, each of the bit lines and each of the source lines having a corresponding column, where each of the bit lines is connected to the drain of the memory cells in the corresponding column and each of the source lines is connected to the source of the memory cells in the corresponding column. Where, in a write operation, the word line corresponding to a selected memory cell is configured to receive a first voltage, and the bit line and the source line of the selected memory cell are configured to receive a second voltage, and where one of the first voltage or the second voltage is a positive voltage and the other of the first voltage or the second voltage is a negative voltage.