The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Dec. 13, 2023
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Maurits Mario Nicolaas Storms, Best, NL;

Jon Scott Choy, Austin, TX (US);

Christopher Nelson Hume, Franklin, TN (US);

Timothy Strauss, Granger, IN (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0613 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01);
Abstract

A non-volatile memory (NVM) includes a daisy chained normal read bus, a daisy chained verify read bus, and a plurality of partitions. Each partition includes a portion of the daisy chained normal read bus and a portion of the daisy chained verify read bus. A memory controller receives read data in response to normal read access requests to the NVM via the daisy chained normal read bus and, in response to write access requests to the NVM, receives verify read data via the daisy chained verify read bus. A bus sharing circuit is coupled between a first partition and a second partition. The bus sharing circuit, in response to a sharing control signal, selectively repurposes portions of the daisy chained verify read bus in at least one of the partitions to communicate read data to the memory controller in response to a normal read access request to the NVM.


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