The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Aug. 04, 2021
Applicant:

Ampere Computing Llc, Santa Clara, CA (US);

Inventors:

Benjamin Crawford Chaffin, Portland, OR (US);

Bret Leslie Toll, Santa Clara, CA (US);

Michael Stephen Chin, Portland, OR (US);

Assignee:

Ampere Computing LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/55 (2013.01); G06F 9/06 (2006.01); G06F 21/52 (2013.01);
U.S. Cl.
CPC ...
G06F 21/554 (2013.01); G06F 9/06 (2013.01); G06F 21/52 (2013.01); G06F 21/556 (2013.01); G06F 2221/033 (2013.01);
Abstract

Mitigation of return stack buffer side channel attacks in a processor. Detecting a side channel attack or a fault in a return from a function call in the processor includes receiving a return exception level indication (or e.g., a return security level indication) indicating the exception level associated with the return and comparing the exception level associated with the return to the exception level (or security level) associated with the return address. The return exception level indicator may be received in conjunction with a return indication. The processing circuit accesses the first entry of the return stack buffer, which indicates the return address of the function call, and also accesses an exception level associated with the return address. The processing circuit compares the exception level associated with the return address to the exception level associated with the return to determine whether to use the return address in a prediction of instruction flow.


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