The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

May. 02, 2023
Applicant:

Sifive, Inc., San Mateo, CA (US);

Inventors:

Cameron Mcnairy, Fort Collins, CO (US);

Michael Klinglesmith, Chambéry, FR;

Assignee:

SiFive, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 11/079 (2013.01); G06F 11/0745 (2013.01);
Abstract

A first circuitry may have a first interface. A response circuitry having a system interface may connect to the first circuitry. The response circuitry may receive an input selection that determines an error handling mode used to respond to an error (e.g., in a lockstep system, the error could be a difference between an output at the first interface and a second output at a second interface identified by comparing the first output to the second output). In some implementations, the error handling mode may cause the response circuitry to provide the output to the system interface and send an indication to software based on detecting the error. In some implementations, the error handling mode may cause the response circuitry to contain at least a portion of the output by disabling at least a portion of the system interface for multiple clock cycles based on detecting the error.


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