The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2025
Filed:
Apr. 04, 2022
Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;
Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;
Jisong Jin, Shanghai, CN;
Abraham Yoo, Shanghai, CN;
Abstract
A semiconductor structure and a method for forming the same are provided. In one form, a semiconductor structure includes: a substrate and protruding portions protruding from the substrate in sub-device regions; channel structure layers located on the protruding portions and spaced apart from the protruding portions, where each of the channel structure layers includes one or more channel layers spaced apart from each other; a dielectric wall located on the substrate between adjacent sub-device regions in a longitudinal direction, where the dielectric wall includes a main dielectric wall portion protruding from the substrate and dielectric wall protrusions protruding from the main dielectric wall portion in the longitudinal direction, where the dielectric wall protrusions are in contact with side walls of the channel layers; gate structures located on the sub-device regions, spanning tops of the channel structure layers in the sub-device regions, and surrounding the channel layers exposed from the dielectric wall; and source/drain doped layers located on the protruding portions on two sides of the gate structures and in contact with the channel structure layers. In forms of the present disclosure, an influence of the dielectric wall on a stress applied by the source/drain doped layers to the channel layers is reduced, and performance of the semiconductor structure is optimized.