The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Dec. 22, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Albert Molina, Novelda, ES;

Kameran Azadet, San Ramon, CA (US);

Martin Clara, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/06 (2006.01); H03M 1/00 (2006.01); H03M 1/68 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1033 (2013.01); H03M 1/0629 (2013.01); H03M 1/002 (2013.01); H03M 1/1014 (2013.01); H03M 1/68 (2013.01);
Abstract

An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.


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