The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Mar. 30, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yuan-Yang Hsiao, Hsinchu, TW;

Hsiang-Ku Shen, Hsinchu, TW;

Wen-Chiung Tu, Hsinchu, TW;

Tsung-Chieh Hsiao, Changhua County, TW;

Chen-Chiu Huang, Hsinchu, TW;

Dian-Hau Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01);
Abstract

A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack. The MIM stack includes at least one lower conductor plate layer, a first insulator layer disposed over the at least one lower conductor plate layer, a first conductor plate layer disposed over the first insulator layer, a second insulator layer disposed over the first conductor plate layer, and a second conductor plate layer disposed over the second insulator layer. The device structure further includes a ground via extending through and electrically coupled to a first ground plate in the first conductor plate layer and a first via extending through and electrically coupled to a high voltage plate in the second conductor plate layer. The first ground plate vertically overlaps the high voltage plate and the second insulator layer is different from the first insulator layer.


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