The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2025
Filed:
Nov. 30, 2021
Intel Corporation, Santa Clara, CA (US);
Norma Bettine, Chandler, AZ (US);
Pavan Kumar, Portland, OR (US);
Justin Tippetts, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Disclosed herein are systems and methods for self-isolation of power-management integrated circuits (PMICs) of memory modules under and in response to fault conditions. In an embodiment, a PMIC is operably engaged with a memory module that is operably engaged with a platform. The memory module includes a non-volatile-memory block having a power supply controlled by the PMIC. The PMIC has a critical-fault signal pin that can be asserted to shut down the platform. The PMIC determines whether at least one critical fault occurred during a prior cycle, and also determines whether a critical fault occurs during a bootup sequence during a current cycle. Based on determining that a prior-cycle critical fault occurred and that a critical fault occurs during the bootup sequence, the PMIC sets a critical-fault indicator corresponding to the current critical fault; powers down the power supply; and does not assert the critical-fault signal pin.