The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Apr. 13, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Po-Chia Lai, Fremont, CA (US);

Shang-Wei Fang, Hsinchu, TW;

Meng-Hung Shen, Hsinchu County, TW;

Jiann-Tyng Tzeng, Hsinchu, TW;

Ting-Wei Chiang, New Taipei, TW;

Jung-Chan Yang, Taoyuan, TW;

Stefan Rusu, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/80 (2025.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 23/485 (2006.01); H01L 23/64 (2006.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10D 84/811 (2025.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 23/485 (2013.01); H01L 23/642 (2013.01); H01L 23/647 (2013.01); H10D 89/10 (2025.01);
Abstract

An integrated circuit is provided, including a first conductive pattern, at least one first conductive segment, and a first via. The first conductive pattern is disposed in a first layer and configured as a terminal of an inverter. The at least one first conductive segment is disposed in a second layer above the first layer and configured to transmit an output signal output from the inverter. The first via contacts the first conductive pattern and the at least one first conductive segment to transmit the output signal. An area, contacting the first conductive pattern, of the first via is smaller than an area, contacting the at least one first conductive segment, of the first via.


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