The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Dec. 14, 2021
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Julien Ryckaert, Schaerbeek, BE;

Naoto Horiguchi, Leuven, BE;

Boon Teik Chan, Wilsele, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/151 (2025.01); H10D 62/235 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

According to an aspect there is provided a FET device. The FET device comprises a common source body portion and a set of source layer prongs protruding therefrom in a first lateral direction. First dielectric layer portions are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion and a set of drain layer prongs protruding in the first lateral direction. Second dielectric layer portions are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion and a set of gate prongs protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong is formed intermediate a respective pair of first and second dielectric layer portions. The device further comprises a channel region comprising a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer prongs. The channel layer portions are arranged in spaces between the gate prongs. There is also provided a method for forming a FET device.


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