The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

May. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chang-Ming Wu, New Taipei, TW;

Wei Cheng Wu, Zhubei, TW;

Shih-Chang Liu, Alian Township, TW;

Harry-Hak-Lay Chuang, Zhubei, TW;

Chia-Shiung Tsai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 21/311 (2006.01); H01L 29/423 (2006.01); H10B 43/30 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01);
U.S. Cl.
CPC ...
H10B 43/30 (2023.02); H01L 21/31116 (2013.01); H10D 30/0413 (2025.01); H10D 30/69 (2025.01); H10D 30/696 (2025.01);
Abstract

A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.


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