The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Feb. 10, 2023
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Santosh Sharma, Austin, TX (US);

Mei Yu Soh, Singapore, SG;

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 17/10 (2006.01); H03K 17/687 (2006.01); H03K 19/00 (2006.01); H03K 19/017 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018535 (2013.01); H03K 17/102 (2013.01); H03K 17/6871 (2013.01); H03K 19/0013 (2013.01); H03K 19/01721 (2013.01);
Abstract

A GaN logic circuit may include an input node receiving an input voltage, a first pull up transistor pulling up an output voltage in response to the input voltage, and a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied. The first depletion mode transistor may control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage. The logic device may further include a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.


Find Patent Forward Citations

Loading…