The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Oct. 20, 2023
Applicant:

Pseudolithic, Inc., Santa Barbara, CA (US);

Inventors:

James Buckwalter, Santa Barbara, CA (US);

Michael Hodge, Huntersville, NC (US);

Justin Kim, San Jose, CA (US);

Florian Herrault, Agoura Hills, CA (US);

Daniel Green, McLean, VA (US);

Assignee:

PseudolithIC, Inc., Santa Barbara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H03H 7/38 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H03H 7/38 (2013.01); H01L 2223/6605 (2013.01); H01L 2223/6661 (2013.01);
Abstract

An electronic assembly has a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks. Chiplets are placed in the cavities. At least one chiplet has a second circuit including at least one transistor or switch device and passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplets and wafer electrically connect the first circuitry to the second circuitry.


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