The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Jun. 20, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Abhijeet Ashok Chachad, Plano, TX (US);

David Matthew Thompson, Dallas, TX (US);

Naveen Bhoria, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01); G06F 9/54 (2006.01); G06F 11/30 (2006.01); G06F 12/0808 (2016.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/084 (2016.01); G06F 12/0895 (2016.01); G06F 12/128 (2016.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 9/3004 (2013.01); G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/3867 (2013.01); G06F 9/467 (2013.01); G06F 9/544 (2013.01); G06F 9/546 (2013.01); G06F 11/3037 (2013.01); G06F 12/0808 (2013.01); G06F 12/0815 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/084 (2013.01); G06F 12/0895 (2013.01); G06F 12/128 (2013.01); G06F 13/1668 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/608 (2013.01);
Abstract

A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.


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