The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2025
Filed:
Mar. 05, 2021
Applicant:
Advantest Corporation, Tokyo, JP;
Inventors:
Assignee:
Advantest Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/319 (2006.01); G01R 31/3177 (2006.01); G06F 9/54 (2006.01); G06F 30/34 (2020.01);
U.S. Cl.
CPC ...
G01R 31/31905 (2013.01); G01R 31/3177 (2013.01); G01R 31/31907 (2013.01); G01R 31/31926 (2013.01); G06F 9/541 (2013.01); G06F 30/34 (2020.01); G05B 2219/13 (2013.01);
Abstract
A method for testing DUT comprises receiving instructions from a system controller at a tester board, wherein the tester board comprises an FPGA and the tester processor are coupled to the system controller, and wherein the tester processor is operable to coordinate testing of a device under test (DUT). The method further comprises generating commands and data for testing the DUT and routing signals associated with the commands and the data in the FPGA based on a type of the DUT. Also, the method comprises transmitting the signals over lanes corresponding to a particular set of pins on the DUT, wherein the particular set of pins depend on the type of the DUT.