The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2025
Filed:
Jun. 15, 2022
Step-stacked nanowire cmos structure for low power logic device and method of manufacturing the same
Samsung Electronics Co., Ltd., Suwon-si, KR;
Samsung Electronics Co., Ltd., Yongin-si, KR;
Abstract
A CMOS device including a substrate comprising a shallow trench isolation region, an nFET on the substrate above the shallow trench isolation region, and a pFET. The nFET includes a source region, a drain region, a channel region including a series of nanowires extending from the source region to the drain region, and a gate region around the series of nanowires of the channel region. The nanowires include a first series of nanowires in a first column and a second series of nanowires in a second column adjacent to the first column. The pFET includes a source region, a drain region, a channel region extending from the source region to the drain region, and a gate region on the channel region.