The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Jun. 22, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Yong-Sheng Huang, Hsin-Chu, TW;

Ming Chyi Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H10D 30/64 (2025.01); H10D 62/13 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 64/256 (2025.01); H10D 30/64 (2025.01); H10D 62/152 (2025.01); H10D 64/017 (2025.01); H10D 64/111 (2025.01); H10D 64/251 (2025.01); H10D 84/013 (2025.01); H10D 84/017 (2025.01); H10D 84/038 (2025.01);
Abstract

A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer comprising a first uppermost surface, a lowermost surface, and a first sidewall surface extending between the uppermost surface and the lowermost surface. A gate dielectric layer is over the semiconductor layer. A first gate electrode is over a portion of the gate dielectric layer over the uppermost surface of the semiconductor layer. A first source/drain region is in the semiconductor layer under the first uppermost surface and adjacent the first gate electrode. A second source/drain region is in the semiconductor layer under the lowermost surface of the semiconductor layer.


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