The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

May. 06, 2023
Applicant:

Huazhong University of Science and Technology, Hubei, CN;

Inventors:

Hao Tong, Hubei, CN;

Binhao Wang, Hubei, CN;

Shaojie Long, Hubei, CN;

Xiangshui Miao, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/68 (2025.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/40 (2023.01);
U.S. Cl.
CPC ...
H10D 1/716 (2025.01); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 41/40 (2023.02);
Abstract

The invention discloses a three-dimensional 1S1C memory based on a ring capacitor and a preparation method. The memory includes: a horizontal peripheral electrode layer including a first dielectric layer and a first metal electrode layer alternately stacked and grown on a substrate and provided with trenches penetrating in a vertical direction and holes penetrating in the vertical direction, a vertical functional layer, and a capacitive dielectric layer. An annular groove is disposed outside each hole. The annular groove surrounds the holes and vertically cuts off the peripheral electrode layer. The annular groove is evenly filled with a capacitive dielectric layer. A top of the second metal electrode layer is extended to a surface of a topmost first dielectric layer to form a bit line electrode and is connected to a bit line. A region where the second metal electrode layer faces the first metal electrode layer forms a memory cell.


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