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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12317500 B1

PDFFull Text
Date of Patent:
May. 27, 2025

Filed:

Jan. 24, 2023

Semiconductor memory device having a contact plug electrically connected to an interconnection through a narrower via

Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventors:

Yoshiaki Fukuzumi, Yokkaichi, JP;

Hideaki Aochi, Yokkaichi, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Younes Boulghassoul

Int. Cl.
CPC ...
H10B 43/40 (2023.01); H01L 21/18 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 43/50 (2023.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); H01L 21/185 (2013.01); H01L 21/76898 (2013.01); H01L 24/80 (2013.01); H01L 25/18 (2013.01); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 43/50 (2023.02); H10D 88/00 (2025.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06541 (2013.01);
Abstract

According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

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