The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Mar. 14, 2024
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventors:

Nyles Wynn Cody, Tempe, AZ (US);

Keith D. Weeks, Chandler, AZ (US);

Robert Michael Vyne, Chandler, AZ (US);

Robert J. Stephenson, Duxford, GB;

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02488 (2013.01); H01L 21/0245 (2013.01); H01L 21/3065 (2013.01); H01L 21/324 (2013.01);
Abstract

A method for making a semiconductor device may include, in an epitaxial deposition tool, performing an anneal on a semiconductor on insulator (SOI) substrate including a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, the second semiconductor layer having a first thickness. The method may also include, in the epitaxial deposition tool, performing an in-situ etch to reduce the second semiconductor layer to a second thickness less than the first thickness, and forming a superlattice layer on the second semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.


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