Apparatuses for timing control in write path

Abstract

Apparatuses for timing control in a write path are disclosed. An example apparatus includes: a clock input circuit that receives a clock signal and provides an internal clock signal; a command decoder that receives command signals and the internal clock signal, and provides an active write command signal when the command signals indicates a write operation; a write latency shifter that receives the write command signal, a latency value and a WICA value, adjusts timing of the write command signal responsive to the latency value and the WICA value, and provides a shifted write command signal; and a write DLL including a delay line that receives the shifted write command signal and provides a delayed write command signal. The write DLL provides the WICA value to set a propagation time from the clock input circuit to the write DLL to be a multiple of a period of the clock signal.