The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Mar. 01, 2023
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Jason Golbus, Santa Clara, CA (US);

Chad Parsons, Santa Clara, CA (US);

Kirk Twardowski, Santa Clara, CA (US);

Lalit Gupta, Santa Clara, CA (US);

Jesse Wang, Santa Clara, CA (US);

Ka Yun Lee, Santa Clara, CA (US);

Amy Chen, Santa Clara, CA (US);

Ramya Challa, Santa Clara, CA (US);

Karan Gupta, Santa Clara, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 8/16 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1048 (2013.01); G11C 7/1075 (2013.01); G11C 8/16 (2013.01); G11C 29/50004 (2013.01); G11C 29/50012 (2013.01); G11C 2029/5004 (2013.01);
Abstract

The disclosure provides improvements for transmitting data between different voltage domains of an IC, such as a chip. The disclosure introduces a data transfer circuit that uses a multi-voltage RAM, referred to herein as MVRAM, for transmitting data across the different voltage domains. The MVRAM has multiple memory cells with write ports and read ports on different clock and voltage domains. Accordingly, a write operation can occur completely on the write domain voltage and the read operation can occur completely on the read domain voltage. In one example, the data transfer circuit includes: (1) write logic operating at a first operating voltage, (2) read logic operating at second operating voltage, and (3) a MVRAM with write ports that operate under the first operating voltage and read ports that operate under the second operating voltage.


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