Memory device and program operation thereof to reduce capacitive coupling

Abstract

Disclosed is a memory device comprising: a memory cell array having a plurality of rows of memory cells; a plurality of word lines coupled to the plurality of rows of memory cells respectively; wherein the memory device is configured to perform programming operations on a target memory cell in the plurality of rows of memory cells, wherein during the programming operations: applying a programming voltage to a selected word line corresponding to a row where the target memory cell locates to program the target memory cell to a target programming state; applying a predetermined voltage to the selected word line to reduce voltage changes caused by capacitive coupling between an unselected word line adjacent to the selected word line and the selected word line; and applying a verification voltage to the selected word line to perform verification operations to verify whether a threshold voltage of the target memory cell is larger than a target threshold voltage corresponding to the target programming state based on the predetermined voltage.