The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2025
Filed:
Aug. 01, 2023
Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;
Boe Technology Group Co., Ltd., Beijing, CN;
Beijing Boe Technology Development Co., Ltd., Beijing, CN;
Mengmeng Du, Beijing, CN;
Yao Huang, Beijing, CN;
Tingliang Liu, Beijing, CN;
Lang Liu, Beijing, CN;
Yuxin Zhang, Beijing, CN;
Xilei Cao, Beijing, CN;
Cong Fan, Beijing, CN;
Zhiwei Xiang, Beijing, CN;
Xiangdan Dong, Beijing, CN;
Hanchao Li, Beijing, CN;
Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan, CN;
BOE Technology Group Co., Ltd., Beijing, CN;
Beijing BOE Technology Development Co., Ltd., Beijing, CN;
Abstract
An array substrate is provided. The array substrate includes a first semiconductor material layer and a second semiconductor material layer on a side of the first semiconductor material layer away from a base substrate. The first semiconductor material layer includes at least active layers of the driving transistor and the data write transistor. The second semiconductor material layer includes at least an active layer of the compensating transistor. A first capacitance is at least partially formed between a gate connecting pad and at least one of the second semiconductor material layer or a first node connecting line. A second capacitance is formed between the first node connecting line and a respective second gate line. The first capacitance is greater than the second capacitance.