The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

May. 05, 2022
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Claudia Roesch, Memmingen, DE;

Balvinder Singh, Haryana, IN;

Murray Glen Shattuck, Jr., Erie, CO (US);

Michael Thompson, Upland, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 2119/02 (2020.01);
Abstract

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design layout and performing parasitic extraction on the electronic design layout. Embodiments may further include extracting an electromagnetic model from the electronic design layout and reconnecting at least one coupling capacitor associated with a net of the electromagnetic model. Embodiments may include performing a simulation including the reconnected at least one coupling capacitor.


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